Sv: Re: Sv: Re: Sv: Re: Sv: Re: data-checksums

On 2018-01-10 00:25:08 +0100, Andreas Joseph Krogh wrote:
> På tirsdag 09. januar 2018 kl. 23:42:45, skrev Rob Sargent <
> robjsargent@gmail.com <mailto:robjsargent@gmail.com>>:
>  
>
>    On 01/09/2018 03:30 PM, Andreas Joseph Krogh wrote:
> På tirsdag 09. januar 2018 kl. 23:06:06, skrev Andres Freund <
> andres@anarazel.de <mailto:andres@anarazel.de>>:
> Hi,
>
>  On 2018-01-09 21:47:17 +0100, Andreas Joseph Krogh wrote:
>  > Does PG use HW-accellerated crc if CPU supports it[1]?
>
>  Yes we do, for WAL checksums. The page checksums are a different
>  algorithm though, one which has the advantage of being SIMD compatible.
>
>  The checksum computations have some impact, but if there's bigger impact
>  it's much more likely to be related to the fact that some hint bit
>  writes to a page now needs to be WAL logged.
>  
> But SIMD-instructions are also HW-accellerated by modern CPUs IIUC?

Sure. Still measurable, but even if weren't, it's irrelevant given my
primary point:

>  The checksum computations have some impact, but if there's bigger impact
>  it's much more likely to be related to the fact that some hint bit
>  writes to a page now needs to be WAL logged.

which isn't mitigated by SIMD / hardware CRC / whatnot.

--

Andreas Joseph Krogh

CTO / Partner - Visena AS

Mobile: +47 909 56 963

andreas@visena.com

www.visena.com