Re: Re: Misaligned BufferDescriptors causing major performance problems on AMD

On Mon, Feb 3, 2014 at 3:38 PM, Andres Freund <andres@2ndquadrant.com> wrote:
>> > A quick hack (attached) making BufferDescriptor 64byte aligned indeed
>> > restored performance across all max_connections settings. It's not
>> > surprising that a misaligned buffer descriptor causes problems -
>> > there'll be plenty of false sharing of the spinlocks otherwise. Curious
>> > that the the intel machine isn't hurt much by this.

>> What fiddling are you thinking of?
>
> Basically always doing a TYPEALIGN(CACHELINE_SIZE, addr) before
> returning from ShmemAlloc() (and thereby ShmemInitStruct).

There is something you have not drawn explicit attention to that is
very interesting. If we take REL9_3_STABLE tip to be representative
(built with full -O2 optimization, no assertions just debugging
symbols), setting max_connections to 91 from 90 does not have the
effect of making the BufferDescriptors array aligned; it has the
effect of making it *misaligned*. You reported that 91 was much better
than 90. I think that the problem actually occurs when the array *is*
aligned!

I suspect that the scenario described in this article accounts for the
quite noticeable effect reported: http://danluu.com/3c-conflict

-- 
Peter Geoghegan