Re: sinval synchronization considered harmful
От | Robert Haas |
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Тема | Re: sinval synchronization considered harmful |
Дата | |
Msg-id | CA+Tgmobxcm9wD7zJgtM3r3EfJQNDc3dD9wYJB5wa9EfxgK7QBQ@mail.gmail.com обсуждение исходный текст |
Ответ на | Re: sinval synchronization considered harmful (Tom Lane <tgl@sss.pgh.pa.us>) |
Ответы |
Re: sinval synchronization considered harmful
Re: sinval synchronization considered harmful Re: sinval synchronization considered harmful |
Список | pgsql-hackers |
On Thu, Jul 21, 2011 at 2:50 PM, Tom Lane <tgl@sss.pgh.pa.us> wrote: > Robert Haas <robertmhaas@gmail.com> writes: >> ... On these machines, you need to issue an explicit memory barrier >> instruction at each sequence point, or just acquire and release a >> spinlock. > > Right, and the reason that a spinlock fixes it is that we have memory > barrier instructions built into the spinlock code sequences on machines > where it matters. > > To get to the point where we could do the sort of optimization Robert > is talking about, someone will have to build suitable primitives for > all the platforms we support. In the cases where we use gcc ASM in > s_lock.h, it shouldn't be too hard to pull out the barrier > instruction(s) ... but on platforms where we rely on OS-supplied > functions, some research is going to be needed. Yeah, although falling back to SpinLockAcquire() and SpinLockRelease() on a backend-private slock_t should work anywhere that PostgreSQL works at all[1]. That will probably be slower than a memory fence instruction and certainly slower than a compiler barrier, but the point is that - right now - we're doing it the slow way everywhere. I think the real challenge is going to be testing. If anyone has a machine with weak memory ordering they can give me access to, that would be really helpful for flushing the bugs out of this stuff. Getting it to work on x86 is not the hard part. -- Robert Haas EnterpriseDB: http://www.enterprisedb.com The Enterprise PostgreSQL Company [1] This was a suggestion from Noah Misch. I wasn't quite convinced when he initially made it, but having studied the issue a lot more, I now am. The CPU doesn't know how many processes have the memory mapped into their address space.
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