Re: SP-GiST micro-optimizations

On Tue, Aug 28, 2012 at 9:42 PM, Tom Lane <tgl@sss.pgh.pa.us> wrote:
> Seems like that's down to the CPU not doing "rep stosq" particularly
> quickly, which might well be chip-specific.

AMD optimization manual[1] states the following:
   For repeat counts of less than 4k, expand REP string instructions
into equivalent sequences of simple
AMD64 instructions.

Intel optimization manual[2] doesn't provide equivalent guidelines,
but the graph associated with string instructions states about 30
cycles of startup latency. The mov based code on the other hand
executes in 6 cycles and can easily overlap with other non-store
instructions.

[1] http://support.amd.com/us/Processor_TechDocs/25112.PDF
[2] http://www.intel.com/content/dam/doc/manual/64-ia-32-architectures-optimization-manual.pdf

Ants Aasma
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