Re: Misaligned BufferDescriptors causing major performance problems on AMD

On 2014-02-05 16:14:01 +0100, Greg Stark wrote:
> I see a lot of confusion online over whether cache lines
> are 64 bytes, 128 bytes, or other length even just on Intel
> architectures, let alone others.

All current x86 processors use 64. But even if it were bigger/smaller,
they will be either 32, or 128. Neither benefits from touching more
cachelines than necessary. E.g. in the 128 case, we could still touch
two with the current code.
The effects referred to upthread only affect code with larger multiples
of the cacheline size. Not what we have here.

> I wonder if there are any generic tools to optimize array/structure
> layouts based on cachegrind profiling or something like that. Then we
> wouldn't need to know the oddities ourselves and optimize manually. We
> could maybe even do it on the build farm and select the right profile
> at build time by matching build target information.

There's profiling tools (e.g. perf's -e
stalled-cycles-(frontent|backend)), but I don't think there's more than
that.
And I think somebody already thought about it (c.f. ALIGNOF_BUFFER), it
just wasn't updated in the last 10 years.

Greetings,

Andres Freund

-- Andres Freund                       http://www.2ndQuadrant.com/PostgreSQL Development, 24x7 Support, Training &
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