Re: Latches with weak memory ordering (Re: max_wal_senders must die)

On Saturday 20 November 2010 00:08:07 Tom Lane wrote:
> Andres Freund <andres@anarazel.de> writes:
> > On Friday 19 November 2010 18:46:00 Tom Lane wrote:
> >> I poked around in the Intel manuals a bit.  They do have mfence (also
> >> lfence and sfence) but so far as I can tell, those are only used to
> >> manage loads and stores that are issued by special instructions that
> >> explicitly mark the operation as weakly ordered.  So the reason we're
> >> not seeing bugs is presumably that C compilers don't generate such
> >> instructions.
> > 
> > Well. Some memcpy() implementations use string (or SIMD) operations which
> > are weakly ordered though.

> Like it says, the cache coherency mechanism prevents this from being a
> problem for us.  Once the change is made in a processor's cache, it's
> the cache's job to ensure that all processors see it --- and on Intel
> architectures, the cache does take care of that.
Check example 8.2.3.4 of 3a. - in my opinion that makes my example correct.

Andres